IBM has entered into a research collaboration with Siemens to accelerate the development and manufacturing readiness of its proprietary nanostack transistor architecture. The partnership pairs IBM’s semiconductor device research with Siemens’ electronic design automation (EDA), TCAD process simulation, lithography optimization, and manufacturing software tools to transition angstrom-scale 3D transistor scaling from laboratory demonstration toward production viability.
Unveiled by IBM earlier this year, nanostack represents an architectural departure from conventional horizontal planar and standard gate-all-around (GAA) nanosheets. As the industry approaches the physical limits of 2D dimensional scaling at the sub-2-nanometer boundary, nanostack shifts device geometries into three dimensions by vertically stacking and staggering nanosheet channels. At its current 7-angstrom (0.7nm) demonstration node, this vertical arrangement packs nearly 100 billion transistors into a footprint the size of a fingernail. Beyond raw transistor density, the multi-tier structure allows engineers to integrate heterogeneous material combinations across stacked layers, optimizing the drive current, threshold voltages, and leakage of individual p-type and n-type transistors independently to accelerate SRAM bitcell scaling.
However, translating complex 3D vertical topologies into repeatable fab processes introduces severe manufacturing hurdles. Multi-level nanosheet channels require high-aspect-ratio etching, atomic-layer deposition across alternating material layers, and complex back-end-of-line (BEOL) metal wiring. To resolve these limitations before running physical silicon wafers, IBM and Siemens are building comprehensive virtual digital twins and predictive models. The joint engineering teams are developing advanced simulation pipelines to evaluate mechanical stress, parasitic capacitances, thermal dissipation, and optical lithography margins for 7-angstrom devices and subsequent sub-nanometer generations.
The initiative addresses the growing need for Design-Technology Co-Optimization (DTCO) across leading-edge foundries. Huiming Bu, Vice President of Silicon Technology R&D at IBM, noted that nanostack establishes a scalable 3D platform to support logic scaling for artificial intelligence infrastructure over the coming decade. Ankur Gupta, Executive Vice President of EDA IC Portfolio at Siemens, emphasized that reaching angstrom-scale dimensions requires synchronous co-design between physical device physics, EDA algorithms, and fab-floor lithography tools.
For the global semiconductor industry, this collaboration establishes the digital design framework needed for next-generation logic chips. By validating lithography recipes and parasitic extraction algorithms early, the partnership lowers first-silicon risk for pure-play foundries and fabless designers preparing to transition beyond nanosheet nodes toward monolithic 3D logic.
