Eliyan has introduced its NuLight™ chiplet platform, presenting what it designates as the semiconductor industry’s first two-dimensional microVCSEL optical interconnect architecture. Unveiled at the OCP Summit, the platform directly targets the physical constraints known as the “copper wall” across hyperscale artificial intelligence clusters. As AI accelerator nodes expand from single-chassis enclosures across multi-rack scale-up domains, conventional copper twinax cabling encounters severe signal attenuation, insertion loss, and thermal density challenges over distances exceeding a few meters.
The NuLight hardware framework comprises two complementary silicon chiplets: Nexus™ and Oscar™. Fabricated on TSMC’s 3nm process node, Nexus functions as a 1.6-terabit-per-second (Tbps) reverse gearbox and retimer. It integrates energy-efficient 212-gigabit-per-second (Gbps) PAM4 SerDes and converts each high-speed serial channel into four slower, parallel non-return-to-zero (NRZ) electrical links. This “slow-and-wide” conversion provides the electrical interface required to drive dense optical arrays without demanding high-overhead per-lane digital signal processing. Nexus also incorporates forward error correction (FEC) regeneration, IEEE auto-negotiation, and link telemetry to monitor channel health.
Complementing the gearbox die, the Oscar chiplet acts as an electrical interface chip (EIC) that houses specialized laser drivers and transimpedance amplifiers (TIAs). Oscar interfaces high-speed electrical signals directly to dense vertical-cavity surface-emitting laser (VCSEL) and photodiode arrays, implementing on-chip crosstalk cancellation and thermal mitigation structures. By utilizing mature Gallium Arsenide (GaAs) microVCSELs rather than complex external Indium Phosphide (InP) laser sources, the architecture delivers an optical reach of approximately 50 meters with power efficiency superior to standard optical transceivers.
System-level reliability represents an acute challenge in massive distributed computing fabrics, where an optical link interruption can stall parallel training runs across thousands of accelerators. To prevent cluster-wide downtime, Eliyan has implemented dynamic on-the-fly lane repair. If an optical path suffers physical degradation, embedded diagnostics automatically reroute data packets to reserved spare lanes without interrupting active communication channels.
The platform provides a modular pathway from pluggable OSFP optical transceivers toward near-packaged optics (NPO) and co-packaged optics (CPO). Future architectural iterations will allow the Oscar interface die to connect directly with host GPUs and custom XPUs via low-latency die-to-die interfaces. By addressing the physical trade-offs separating copper economics from optical reach, Eliyan’s 2D microVCSEL chiplets offer an alternative interconnect paradigm for high-bandwidth AI infrastructure.
