French research institute CEA, alongside electronic design automation (EDA) specialist Defacto Technologies and workflow provider Innova Advanced Technologies, announced the release of SoC PLANNER for early adopters. Supported by Bpifrance under the France 2030 program, the three-year R&D initiative delivers an integrated front-end framework that unifies architectural planning, automated design-space exploration (DSE), and register-transfer-level (RTL) code generation into a single continuous environment.
Modern system-on-chip (SoC) engineering faces mounting friction. Complex architectures designed for high-performance computing (HPC), automotive systems, and edge acceleration present millions of viable parameter permutations. Traditional semi-manual architectural evaluation struggles to navigate the trade-offs between power, performance, and area (PPA) within tight tape-out schedules. SoC PLANNER addresses this bottleneck by replacing fragmented exploration scripts with an autonomous, multi-objective design engine.
A Unified Front-End Pipeline
The platform consolidates three core technologies into an automated pipeline:
Exploration Engine (CEA A-DECA): Evaluates multi-variable design parameters via analytical models, system simulation, and lightweight AI optimization to pinpoint Pareto-optimal trade-offs.
Silicon Implementation (Defacto SoC Compiler): Automatically constructs synthesizable, implementation-ready RTL directly from selected architectural definitions, removing manual translation errors.
Process Orchestration (Innova PDM): Manages design data integrity, computational compute workloads, and workflow execution across exploration cycles.
Architects define their parametric boundaries, power and latency budgets, and target KPIs. The platform’s search algorithms map the design space, assess hardware efficiency, and immediately synthesize the chosen configurations into RTL.
A key technical addition to this flow is an integrated eco-design metric. Alongside conventional PPA analysis, SoC PLANNER calculates an environmental footprint score for each architectural variant, establishing carbon and energy impact as measurable design constraints during early front-end planning.
Industrial Validation
The framework was benchmarked across two high-complexity hardware designs:
Configurable AI Accelerator: The tool executed automated multi-objective exploration to balance inferencing latency against die area and thermal constraints, generating verified RTL for the optimal layout.
Next-Generation HPC Processor: Applied to system-level exploration on the European Rhea processor platform, the engine assessed thousands of architectural configurations to validate cache hierarchies, interconnect throughput, and power dissipation.
Silicon evaluations demonstrated a 30% to 40% reduction in front-end exploration cycles compared to conventional engineering flows. By tightly coupling high-level design exploration directly to downstream RTL generation, the platform eliminates typical handoff disconnects.
SoC PLANNER is currently open to early-access commercial design teams developing high-density computing platforms that demand aggressive PPA targets and verifiable sustainability reporting.
