Arteris, Inc. has announced the expansion of its third-party IP (3PIP) security assurance program in collaboration with BAE Systems and SiFive, Inc., securing an additional $3.3 million in funding under the Trusted and Assured Microelectronics (T&AM) program. The initiative, overseen by the Office of the Under Secretary of Defense for Research and Engineering, focuses on establishing standardized, evidence-based methodologies to verify the integrity and trustworthiness of commercial silicon intellectual property before integration into mission-critical systems-on-chip (SoCs).
Modern semiconductor systems rely extensively on commercial off-the-shelf IP blocks to accelerate development cycles and manage architectural complexity. However, incorporating external processing cores, interfaces, and interconnect fabrics into defense and mission-critical hardware introduces severe supply-chain exposure. Undetected design vulnerabilities, non-standard bus behaviors, or undocumented registers can compromise entire microelectronic systems. The joint project between Arteris, BAE Systems FAST Labs, and SiFive addresses this exposure by creating a repeatable verification protocol that audits commercial IP directly within complex SoC environments.
The technical collaboration targets the intersection of processor architectures, interconnect fabrics, and defense-grade verification. SiFive brings its open-standard RISC-V processor IP portfolio to the initiative, while BAE Systems FAST Labs provides operational guidance and threat models tailored to defense platforms. Arteris provides its Common Weakness Enumeration (CWE)-based microelectronics evidence framework. This methodology correlates documented hardware vulnerabilities to verifiable functional properties and rigorous coverage metrics, tracing security behavior across IP blocks, subsystems, chiplets, and software-driven SoCs during pre-silicon design phases.
By establishing measurable, pre-silicon verification benchmarks, the program addresses a fundamental bottleneck in trusted hardware manufacturing. Moving away from reactive post-silicon testing toward pre-tape-out assurance allows chip architects to eliminate architectural vulnerabilities before incurring high fabrication costs. This structured validation framework aligns directly with ongoing domestic efforts to harden the microelectronics supply chain against side-channel vulnerabilities, logic flaws, and unauthorized silicon modifications.
While designed to support defense modernization, the verification framework has wide-ranging implications for commercial semiconductor markets. High-reliability applications such as autonomous vehicles, data center accelerators, and edge robotics face similar supply-chain integrity demands as they integrate multi-vendor chiplets and heterogeneous IP. Standardizing third-party silicon security assurance provides engineering teams with the technical criteria necessary to integrate diverse commercial IP blocks while maintaining rigorous hardware trustworthiness.
