Siemens has expanded its collaboration with NVIDIA to accelerate computational lithography workflows by integrating NVIDIA cuLitho—a CUDA-X software library engineered for GPU-accelerated lithography—directly into its Calibre® manufacturing software platform. The integration targets the severe runtime limitations of advanced optical proximity correction (OPC) and inverse lithography technology (ILT), enabling semiconductor foundries and photomask manufacturers to scale full-chip curvilinear patterning for next-generation artificial intelligence processors.
As leading-edge logic and high-density memory nodes transition toward High-NA Extreme Ultraviolet (EUV) lithography, feature sizes shrink well below optical limits. Compensating for diffraction effects, light scattering, and optical distortions requires massive mathematical modeling. Traditional CPU-based computational lithography environments have encountered an operational runtime wall. Advanced techniques such as curvilinear ILT generate arbitrary, non-Manhattan mask shapes to maximize process windows, but their computational complexity has historically forced engineering teams to balance simulation depth against tapeout deadlines. This compromise elevates the risk of post-tapeout lithographic hotspots and reduces fabrication margins across advanced fabs.
The integration of cuLitho with Siemens Calibre removes this computational bottleneck by offloading parallel simulation workloads to graphics processing units. Verified benchmark data demonstrates acceleration factors ranging between 10x and 17x across critical computational lithography and full-chip OPC tasks. Ankur Gupta, Executive Vice President of EDA IC Portfolio at Siemens, emphasized that coupling signoff-grade Calibre engines with GPU acceleration allows semiconductor manufacturers to execute curvilinear ILT at high-volume production scale rather than limiting it to localized test macros. Tim Costa, Vice President and General Manager of Industrial and Computational Engineering at NVIDIA, noted that the joint architecture enables engineers to handle increasingly complex geometric patterns and explore deeper optimizations required for leading-edge silicon fabrication.
For commercial wafer fabs and merchant mask shops, compressing computational runtimes provides direct operational and yield advantages. Process integration engineers can run significantly more design iterations in shorter timeframes, detecting optical and resist hotspots prior to photomask write operations. Because producing High-NA EUV reticle sets involves substantial capital expense and long electron-beam write times, eliminating patterning errors pre-silicon protects fab capacity and improves wafer yields during volume ramps.
The breakthrough reinforces the critical intersection of electronic design automation, accelerated computing, and physical wafer processing. As chipmakers pursue sub-2nm nodes and 3D heterogeneous packaging, materials interactions and optical boundaries demand high-performance computing at every step of design-to-manufacturing handoffs. By embedding GPU acceleration into Calibre’s industry-standard verification environment, Siemens and NVIDIA have made full-chip curvilinear lithography commercially viable, providing the patterning precision required to manufacture advanced AI accelerators and high-bandwidth memory.
