Taiwan Semiconductor Manufacturing Co. (TSMC) is planning to expand its footprint into the Baipu Industrial Park in Kaohsiung. The proposed project aims to accelerate the testing and validation of advanced semiconductor materials and manufacturing equipment, directly targeting severe packaging bottlenecks created by the global artificial intelligence boom.
TSMC Vice President of Advanced Packaging Technology and Service Jun He outlined the initiative at a global 3D IC summit ahead of SEMICON Taiwan. Under the plan, TSMC will collaborate with Taiwan’s Ministry of Economic Affairs and the Kaohsiung City government to establish a dedicated hub expected to boost validation efficiency by 25% to 50%.
Modular Infrastructure for 3D IC Innovation
TSMC’s plan involves developing a 3-hectare site featuring two specialized buildings designed with modular, reconfigurable architecture. The facility will house cleanrooms and laboratories dedicated to process research and development (R&D), joint component validation, and advanced packaging innovation.
As physical transistor scaling under traditional Moore’s Law slows, advanced packaging—notably TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) and 3D integrated circuit (3D IC) architectures—has become central to chip performance. Modern AI accelerators rely on packaging multiple discrete dies and high-bandwidth memory into dense systems. By implementing modular cleanrooms, TSMC intends to reconfigure equipment lines rapidly as packaging architectures evolve.
Beyond testing, the proposed complex is designed to operate as a world-class training center for advanced packaging engineers and technicians. It will also provide domestic and international suppliers a dedicated environment to test hardware, software, and materials under live conditions before integrating them into mass-production fabs.
Scaling Packaging Capacity for AI Workloads
The expansion blueprint addresses explosive demand from AI accelerators, high-performance computing (HPC), and 5G networks, which continue to outpace existing backend capacity. TSMC projects its CoWoS advanced packaging capacity to expand at a compound annual growth rate (CAGR) of over 80% through 2027, with double-digit growth anticipated through 2029.
To support this aggressive roadmap, TSMC approved a capital budget of approximately $29.44 billion to fund capacity expansion and fabrication facility construction. The company also raised its full-year capital expenditure forecast to between $60 billion and $64 billion, up from an earlier projection of $52 billion to $56 billion, citing sustained compute demand.
By planning this testing and R&D hub near its growing fabrication ecosystem in Kaohsiung, TSMC seeks to shorten the feedback loop between equipment vendors and foundry production. Accelerating validation from months to weeks will allow the chipmaker to qualify next-generation materials faster and protect its manufacturing leadership in AI silicon.
